module tt #(
		parameter	DATA_WIDTH	=32,
		parameter 	ADDR_WIDTH	=13


)
(
                           // inputs:
                            address,
                            byteenable,
                            chipselect,
                            clk,
                            clken,
                            reset,
                            write,
                            writedata,

                           // outputs:
                            readdata
                         );


 


  output  [ 31: 0] readdata;
  input   [ ADDR_WIDTH-1: 0] address;
  input   [  3: 0] byteenable;
  input            chipselect;
  input            clk;
  input            clken;
  input            reset;
  input            write;
  input   [ 31: 0] writedata;

  wire    [ 31: 0] readdata;
  wire             wren;
  assign wren = chipselect & write;
 
dual_port_ram
#(
 .DATA_WIDTH		(DATA_WIDTH),
 .ADDR_WIDTH 		(ADDR_WIDTH)
 )
 the_nios_ram
(
	.clk		(clk),
	
	.data_a	(writedata),
	.addr_a	(address),
	.we_a		(wren),
	.q_a		(readdata),
	
	.data_b(),
	.addr_b(),
	.we_b(),
	.q_b()
	
	
);

 endmodule
 